1. Field of the Invention
The present invention relates generally to silicon-on-insulator metal-oxide-semiconductor (SOI-MOS) devices and manufacturing method thereof and, more particularly to such devices having a novel sidewall structure to improve operating characteristics thereof.
2. Description of the Background Art
Generally, a field effect transistor with source and drain regions formed on a surface of such semiconductor substrate as silicon is referred to as a bulk MOS. Another structure of a field effect transistor is a SOI-MOS structure in which source, drain and channel regions are formed in a silicon thin film on an insulating substrate such as sapphire or an insulating thin film.
The bulk MOS has the following drawbacks as compared with the SOI-MOS. First, in the CMOS structure, an n type substrate region or an n type well of a pMOS and a p type substrate region or a p type well of an nMOS form a pn junction, there exist parasitic bipolar transistors. In this case, two bipolar transistors of pnp and npn exist to form a parasitic pnpn thyristor. Therefore, there occurs a phenomenon that the thyristor remains conductive and is not restored due to an effect such as an external noise, that is, latch-up is generated. A distance between the pMOS and nMOS can not be made too short because in order to prevent the latch-up, gains of the bipolar transistors forming the parasitic pnpn thyristor should be reduced. Accordingly, with the bulk MOS structure, integration density of a transistor has its limit.
In addition, in the bulk MOS structure, all of the source and drain regions have pn junctions formed between the same and substrates or wells. Therefore, the parasitic capacitance by the pn junction is a disadvantageous factor in a high speed operation of the transistor.
FIG. 7 is a sectional view showing a conventional general SOI-MOS. Referring to FIG. 7, a SOI-MOS comprises, for example, an island-shaped p-type semiconductor layer 3 having an insulated periphery on an insulating substrate 2 of sapphire or the like. An n.sup.+ source region 31 and an n.sup.+ drain region 32 isolated from each other are provided in the semiconductor layer 3 so as to reach an interface between the semiconductor layer 3 and the insulating substrate 2. A gate electrode 7 of polycrystalline silicon or the like is provided on a channel region 33 between the source and drain regions 31 and 32 through a gate oxide film 6.
Thus, in a SOI-MOS structure, perfect isolation among transistors is possible. With a CMOS (Complementary Metal Oxide Semiconductor) structure, even if an n-type region and a p-type region is close, generation of latch-up is prevented and parasitic capacitance is reduced so that if a highly reliable semiconductor device is provided, which has attracted attention. Recently, a principal is known that if a thickness of a silicon layer formed on an insulating substrate becomes below 0.1 .mu.m, characteristics such as a current drivability capability and short-channel effect are improved due to a fully depleted channel region. This is reported in a published paper by J. P. Colinge et al. entitled "CMOS circuits made in thin SIMOX films" in Electronics letters vol. 23 pp. 1162-1164 (1987). Therefore, the SOI-MOS is expected as a basic structure of a transistor of submicron order.
In order to practically obtain the above described characteristics, each SOI-MOS transistor can be isolated by LOCOS (Local Oxidation of Silicon) method or mesa-type isolation method.
FIG. 8 is a partially sectional view showing a structure of a SOI-MOS transistor isolated by the LOCOS method. Referring to FIG. 8, an insulating layer 2 is formed on a silicon substrate 1. A single-crystalline silicon layer 3 is formed on the isolating layer 2. A thick isolating oxide film 40 is formed on the single-crystalline silicon layer 3 so as to isolate active regions spaced apart from each other. A source region 31, a drain region 32 and a channel region 33 are formed in the single-crystalline silicon layer 3 as an active region. A gate electrode 7 is formed on the channel region 33 through a gate oxide film 6. An aluminum interconnection layer 10 is formed on respective surfaces of the source region 31, the gate electrode 7 and the drain region 32. The isolated structure by the LOCOS method is not suitable for isolation of the elements of a miniaturized SOI-MOS since the isolating oxide film 40 extends greatly in lateral direction to form sometimes called a bird's beak.
FIG. 9 is a partially sectional view showing a SOI-MOS having its elements isolated by the mesa-type isolation method. Referring to FIG. 9, single-crystalline silicon layers 3 separated from each other are formed on an insulating layer 2. An interlayer insulating film 9 fills up spaces between these single-crystalline layers 3 through a thin insulating film 4 so as to isolate each single-crystalline silicon layer 3. A source region 31, a drain region 32 and a channel region 33 are formed in the single-crystalline silicon layer 3. A gate electrode 7 is formed on the channel region 33 through a gate oxide film 6. An aluminum interconnection layer 10 is formed on respective surfaces of the source region 31, the drain region 32 and the gate electrode 7. Such a mesa-type isolated structure can be precisely processed according to a resist pattern using a photolithography technique. Therefore, the mesa-type isolation method is suitable for a method of isolating more and more miniaturized SOI-MOS transistors. However, with the mesa-type isolation method, as shown in FIG. 10, a parasitic MOS transistor can be formed on a sidewall or a corner portion 3a, 3b of the single-crystalline silicon layers 3.
FIG. 10 is a partially sectional view perpendicular to the section shown in FIG. 9, and a partially sectional view showing a section in a direction along to a channel width. A single-crystalline silicon layer 3 is formed into an island-shaped configuration so as to extrude from an insulating layer 2. Thus, a gate electrode 7 is formed through a gate oxide film 6 not only on an upper surface but on side surfaces of the single-crystalline silicon layer 3. At this time, when a voltage is applied to the gate electrode 7, a parasitic MOS transistor is formed on the side surfaces 3a and 3b along a direction of a channel length of the single-crystalline silicon layer 3.
As described above, when a parasitic MOS transistor is formed, characteristics of drain current-gate voltage become defective within the range shown by P as shown in FIG. 11. This is caused by the fact that formation of a parasitic MOS transistor on a sidewall surface of the single-crystalline silicon layer causes a leak current to flow between a source and a drain at a relatively low gate voltage. In order to resolve the problem, a threshold voltage V.sub.th of normal transistor should be made larger by increasing impurity concentration of a whole channel region 3c in FIG. 10 and the like. However, increased threshold voltage V.sub.th causes a reduction of an effective voltage {=(supplied voltage)-(threshold voltage)}, which in turn requires a reduction of drain current of a SOI-MOS transistor.
A structure of a SOI-MOS transistor directed to solve the above described problem is disclosed in Japanese Patent Laying Open No. 62-298162. FIG. 12 is a partial plan view showing a plane arrangement of the SOI-MOS disclosed in the above described official gazette, FIG. 13 is a partially sectional showing a section taken along a line XIII--XIII in FIG. 12. Referring to FIGS. 12 and 13, a single-crystalline silicon layer 3 is formed on an insulating substrate 2. A gate oxide film 6 is formed on an upper surface of the single-crystalline silicon layer 3, and thin insulating film 4 is formed on a side surface of the single-crystalline layer 3. A polycrystalline silicon layer 52 in which a p-type impurity is introduced is formed on a periphery of the single-crystalline silicon layer 3 so as to surround it through the insulating film 4. An insulating film 61 is formed on an outer surface of the polycrystalline silicon layer 52. A gate electrode 7 extends over the gate oxide film 6 and the insulating film 61. The gate electrode 7 is connected to a interconnection layer 71. A source region 31 and a drain region 32 are formed in the p-type single-crystalline silicon layer 3 by introduction of n-type impurity. The source region 31 and the p-type single-crystalline silicon layer 52 are connected to an interconnection layer 10 through a contact hole 11, whereby potentials of the source region 31 and the polycrystalline silicon layer 52 are held the same. The drain region 32 is connected to an interconnection layer 10 through a contact hole 12. According to the above described structure, since a potential of the p-type polycrystalline silicon layer 52 formed on the sidewall of the single-crystalline silicon layer 3 is held the same as that of the source region 31, the side surface of the single-crystalline silicon layer 3 is never converted to be an inversion layer nor depletion layer. Therefore, a leakage current between the source and drain flowing through the side surface along the direction of a channel length can be prevented.
On the other hand, another structure of the SOI-MOS transistor directed to prevent a leak current of the sidewall as in the foregoing is disclosed in Japanese Patent Laying-Open No. 59-181670. FIG. 14 is a partial plan view showing a plane arrangement of the SOI-MOS transistor as disclosed, FIG. 15 is a partially sectional view taken along a line XV--XV in FIG. 14, and FIG. 16 is a partially sectional view taken along a line XVI--XVI in FIG. 14. Referring to FIGS. 15 and 16, a single-crystalline silicon layer 3 is formed on an insulating substrate 2. A source region 31 and a drain region 32 of n.sup.+ impurity regions are formed in the single-crystalline silicon layer 3 as shown in FIGS. 14 and 16. A gate electrode 7 is formed on a channel region 33 through a gate oxide film 6 as shown in FIGS. 15 and 16. A polycrystalline silicon layer 52 in which p-type impurity is introduced is formed on a sidewall of the single-crystalline silicon layer 3 through insulating film 4 as shown in FIGS. 14 and 15. Referring to FIG. 16, an aluminum interconnection layer 10 is connected to the source region 31 and the drain region 32 through contact holes formed in an interlayer insulating film 9. In this structure, in order to hold potentials of the source region 31 and the polycrystalline silicon layer 52 the same, concaves 4a are formed in the thin insulating film 4 as shown in FIG. 14. The source region 31 and the polycrystalline silicon layer 52 are connected through the concaves 4a.
However, even if a leak current generated on the sidewall can be reduced as described above, the following problems shown in FIG. 17 cannot be resolved.
As a SOI-MOS transistor is miniaturized, increase of a drain voltage causes an electric field in a channel direction to become significantly large near the drain especially in a short channel MOS transistor. As a result, electrons (a in FIG. 17) injected from source region in the channel region are accelerated by the strong electric field to easily enter a high energy state. The high energy electrons collide with silicon atoms near end portions of the drain region, whereby a greater number of pairs of electron and hole are generated as shown in FIG. 17. Among the electrons and holes generated by the impact ionization (b in FIG. 17) as described above, electrons are attracted to a higher drain electric field to flow into the drain region and becomes a part of a drain current. The holes are drawn back inversely by the drain electric field to flow into a depletion layer under the channel region or the source region (c in FIG. 17). Such phenomenon is observed not only in a short-channel MOS transistor but also in a relatively long-channel MOS transistor. Especially in the short-channel MOS transistor, overwhelmingly large number of pairs of electron-hole are generated as compared in the long-channel MOS transistor.
When the holes thus generated by impact ionization flow into the depletion layer under the channel region, the holes cause potentials near the channel region and the source region to rise so that a height of a potential barrier is lowered. When the potential barrier near the source region is lowered, a lot of electrons are implanted from the source region into a substrate region or the channel region, thereby impact ionization becomes more and more active, so that more pairs of electron and hole are generated. The generated holes cause the potential barrier near the source region to be lowered furthermore and the electrons implanted from the source region to be more and more increased. Thus, the MOS transistor finally breaks down.
Since in the SOI-MOS structure, a MOS transistor is formed on an insulating substrate or film, a substrate region of the MOS transistor is floated. Therefore, as described above, as the drain voltage is increased, holes (in case of nMOS among pairs of electron and hole generated by the impact ionization of channel carriers stay in the substrate region and bias the same to be positive, thereby dropping the threshold voltage, resulting in the sudden increase of the drain currents. A potential of the substrate region of the SOI-MOS transistor is made unstable in this way. This phenomena is referred to as a substrate floating effect. In addition, the above described impact ionization is generated also near the end portion of the drain region due to a small amount of the leak current between the source and drain.